1. Field of Invention
This invention relates to an integrated circuit (IC) process, and more particularly relates to a double patterning process.
2. Description of Related Art
Along with the rapid development of the IC industry, the requirement on device integration unceasingly gets higher, so the dimensions of devices and the pitch of device patterns always have to be reduced. The pattern pitch can be reduced by increasing the lithographic pitch resolution, but such an increase usually costs much. To overcome the pattern-density limitation caused by the pitch resolution, the so-called double patterning technique is proposed to increase the integration degree of devices.
In a double patterning process, two cycles of photoresist coating, exposure and development are performed over a mask layer to transfer two different sets of patterns onto the mask layer. Thus, the pitch of the total patterns can be smaller than the pitch resolution value of a single exposure process.
However, because the distribution of the first set of patterns defined from the first photoresist layer is not uniform over the memory cell area and the peripheral area of the substrate, the thickness of the second photoresist layer as coated is not uniform in the cell area. As a result, the accuracy of the pattern transfer to the second photoresist layer and the underlying target layer is lowered. Thus, a method capable of uniformly coating the second photoresist layer in a double patterning process is desired.